Method and Layout of Semiconductor Device with Reduced Parasitics

ABSTRACT

An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection.

TECHNICAL FIELD

This invention relates generally to semiconductor devices, and more particularly to devices with reduced parasitics.

BACKGROUND

While semiconductor devices have been used in electronic devices such as computers and cellular phones, semiconductor devices are also increasingly used for high power and high frequency applications such as subscriber cable service transmission and cellular base station transmission. Therefore, one of the goals of the semiconductor industry is to develop semiconductor devices that operate at high frequencies as well as provide adequate power for data transmission applications.

One type of semiconductor device used for high power and high frequency applications is the power metal oxide field effect transistor (MOSFET). Of the various forms of power MOSFETs, the Lateral Double-Diffused Metal Oxide Semiconductor (LDMOS) device is commonly used because of its output power capability and high efficiency. Because of its high performance and efficiency, the LDMOS device has found its way into demanding applications such as cellular phone base stations and other transmission equipment.

As performance requirements have become more demanding, however, semiconductor device manufacturers must continually improve power transistor device performance. One limitation to power transistor device performance is parasitic capacitance. In power transistors, parasitic capacitance is particularly problematic because of the large device structures necessary to source and sink large currents, while avoiding breakdown at high voltages. As device size increases, parasitic capacitance contributors, such as source-substrate capacitance, drain-substrate capacitance, gate-drain capacitance, gate-source capacitance, and interconnect capacitance also increase.

Besides limiting device performance through the mere presence of capacitive loading, practical considerations in dealing with parasitic capacitance may also lead to higher resistive parasitics. For example, in order to maintain a minimum parasitic gate-source capacitance due to the presence of gate routing over the source, the number of gate contacts may have to be reduced. Such a reduction in the number of gate contacts results in a correspondingly higher series gate resistance.

In the field of highly efficient power transistors, device structures that minimize parasitic capacitance are needed.

SUMMARY OF THE INVENTION

In one embodiment of the present invention, a semiconductor device is provided. The device includes a layer of insulating material disposed over a semiconductor body, and a gate electrode disposed over the layer of insulating material. The gate electrode comprises a first region of gate electrode material having a length, width, a first end at an end of the length and a second end at end of the length opposite the first end. The device also includes a source region disposed within the semiconductor body adjacent to the first region of gate electrode material along the width of the first gate region of gate electrode material. Similarly, the device includes a drain region disposed within the semiconductor body adjacent to the first region of gate electrode material along the width of the first region of gate electrode material opposite the source region. A gate connection comprising a second region of gate electrode material that extends away from the width of the first gate region is provided. The gate connection is electrically coupled to a contact region and to a region of gate electrode material along the width of the first region of gate electrode material between the first and the second end. A first insulating region disposed beneath the gate connection.

The foregoing has outlined rather broadly features of the present invention. Additional features of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIGS. 1 a-1 c illustrate a layout view and corresponding cross-sections of an embodiment of the present invention;

FIGS. 2 a-2 b illustrate a layout view and corresponding cross-sections of an alternate embodiment of the present invention;

FIGS. 3 a-3 b illustrate a layout view and corresponding cross-sections of another embodiment of the present invention; and

FIGS. 4 a-4 b illustrate a layout view and corresponding cross-sections of an additional embodiment of the present invention.

Corresponding numerals and symbols in different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. To more clearly illustrate certain embodiments, a letter indicating variations of the same structure, material, or process step may follow a figure number.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that may be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

The invention will now be described with respect to preferred embodiments in a specific context, namely a semiconductor device with reduced parasitics. Concepts of the invention can also be applied, however, to other electronic devices.

Referring first to FIG. 1 a, a layout view of two symmetric LDMOS transistor pairs 100 and 101 is shown. In a preferred embodiment of the present invention, each transistor within LDMOS transistor pairs 100 and 101 includes a source region 106, a drain region 108, and a gate region 103. Each transistor pair 100 and 101 further includes shared common drain contacts 114, drain routing 112, and a doped drain contact region 110 that provides a low resistance electrical connection to drain regions 108.

Gate contacts 115 provide electrical coupling from a metallization layer (not shown) to the gate regions 103 of the devices. Gate regions 103 are coupled to gate contacts 115 by a region of gate electrode material 102 that is made from the same material as gate region 103. In a preferred embodiment of the present invention, field plate 116 is provided to shield gate region 103 from drain region 108, which reduces the amount of gate-drain capacitance. Excess gate-drain capacitance is undesirable in most common source LDMOS applications because of the Miller multiplication effect.

Turning to FIG. 1 b, a cross section 150 taken at line 1 b-1 b of FIG. 1 a is shown illustrating symmetric n-channel LDMOS transistor pair 100. In a preferred embodiment of the present invention, drain regions 108 are lightly doped n-type regions, and are electrically connected to a shared drain contact 114. Shared drain contact 114 is typically coupled to drain region 108 by a tungsten via 138 above doped drain contact region 110 and intervening barrier layers 136 and 140. In a preferred embodiment of the present invention, doped drain contact region 110 is doped at a higher concentration than drain region 108 to provide for a lower resistance connection to drain contact 114. The drain region 108 and drain contact region 110 are fabricated according to conventional techniques known in the art. In alternative embodiments of the present invention, the LDMOS device may be p-type, and consequently drain regions 108 would be p-type regions. In yet other alternative embodiments, non-lightly doped regions may be present, barrier layers 136 and 140 may not necessarily be present, drain regions 108 may or may not be shared, and other materials besides tungsten may be used in forming via 138.

Source regions 106 are preferably p-type regions disposed within p-well regions 124, which are disposed within a p-type epitaxial layer 128 at the surface of substrate 130. Source regions 106 are electrically coupled to metal layer 132 on the back side of the substrate 130 through an ion implanted p+ sinker 126 in series with substrate 130. In a preferred embodiment of the present invention, source regions 106 do not have contacts on the top surface of the top surface. Rather, the source connection is made though the back of the substrate. In a preferred embodiments of the present invention, substrate 130 is a low resistivity substrate, typically about 10 Ωcm. Sinker 126 and epitaxial layer 128 can be fabricated using conventional methods. In alternative embodiments, however, contact to source region 106 can be made from the topside of substrate 130 rather than from the bottom of substrate 130. In yet other embodiments of the present invention, source regions 106, well regions 124, and possibly epitaxial layer 128 can be made from n-type material in order to create a p-type LDMOS device.

Gate regions 103 disposed within oxide layer 134 are preferably made from polysilicon using conventional methods. In some preferred embodiments this gate can be a two-layer gate including a polysilicon layer on the bottom and a titanium silicide layer on top, although in other embodiments of the present invention, other materials may be used. For example, cobalt silicide, nickel silicide, and tungsten silicide can be used. In other embodiments of the present invention, a polysilicon/tungsten nitride/tungsten gate stack can be used which utilizes non-silicided gate materials. Titanium silicide, however, is a preferred material for the fabrication of power devices. Field plate 116 is preferably formed adjacent to gate region 103 in order to shield gate region 103 from drain region 108 and via 138. Field plate 116 is preferably made from metal and is formed using conventional methods. In alternative embodiments of the present invention, however, field plate 116 may be omitted.

Turning to FIG. 1 c, a cross-section 152 taken at line 1 c-1 c of FIG. 1 a is shown illustrating symmetric LDMOS transistor pair 100. The cross-section shows gate region 103 electrically coupled to gate contact 115 through via 142, barrier layer 136 and gate connection region 102. In a preferred embodiment of the present invention, via 142 is made from tungsten, and gate connection region 102 is formed from the same materials as gate region 103 as described herein above using conventional methods. In alternative embodiments of the present invention, other materials may be used.

In the conventional LDMOS devices, gate connection region 102 would overlie source regions 106 creating excess gate-source capacitance. In the preferred embodiment of the present invention, however, STI regions 104 are formed underneath gate connection region 102. The presence of STI region 104 (region 104 a in FIG. 1 a) reduces the gate-source capacitance compared to a conventional embodiment. In conventional embodiments, the number of gate contacts are typically limited by the maximum level of tolerable gate-source capacitance. Excess gate-source capacitance limits the high frequency performance of the LDMOS device. By reducing the gate-source capacitance in the manner described hereinabove, more gate connection regions 102 can be provided for a given maximum gate-source capacitance. As a result of having more gate connection regions 102 in parallel, the overall series input resistance for a given parasitic input capacitance will be reduced, thereby improving both the high frequency performance of the LDMOS device as well as the noise performance.

In a preferred embodiment of the present invention, STI regions 104 are trenches filled with high-density plasma oxide at a depth of about between about 200 nm and about 1000 nm, preferably 300 nm to 700 nm, using conventional methods. Because STI regions 104 contain insulating material, they present a much higher impedance to any adjoining semiconductor region or metal layer than epitaxial layer 128 or substrate 130. As a result of its higher impedance, STI regions 104 present a lower capacitive load than epitaxial layer 128 or substrate 130. In alternate embodiments of the present invention, other materials and other depths may be used.

In order to further reduce parasitic capacitance, such as drain-substrate, source-substrate, and gate-substrate capacitance, STI region 104 b of FIG. 1 a is formed against the ends of the device. The presence of STI region 104 b places source region 106 and drain region 108 adjacent to an STI region rather than adjacent to epitaxial region 128 as typically done in the conventional designs. Consequently, capacitance from source region 106 and drain region 108 to the epitaxial region 128 is lower than a corresponding conventional structure. By disposing gate overhang regions 105 over STI region 104 b instead of over a epitaxial region 128, parasitic gate-substrate capacitance is further reduced compared to conventional designs.

Turning to FIG. 2 a, a layout view of another preferred embodiment of the present invention is shown. This embodiment of the present invention is similar to the embodiment shown in FIGS. 1 a-1 c, except that STI regions 104 a on opposite sides of device pairs 100 and 101 are joined together such that STI regions 104 a bisect device pairs 100 and 101. This extension of STI regions 104 a partially isolates drain regions 108 from the possibility of increased gate-drain capacitance from gate connection region 102.

FIG. 2 b shows a cross-sectional view of a preferred embodiment of device pair 154 taken at cross-sectional line 2 b-2 b of FIG. 2 a. As shown, STI region 104 underlies gate connection regions 102, gate regions 103, field plates 116, and oxide region 134 between gate regions 103. STI region 104 presents a lower capacitive load to gate connection regions 102 and gate regions 103 than to source regions 108 (see FIG. 2 a).

Turning to FIG. 3 a, a layout view of another preferred embodiment of the present invention is shown. This embodiment of the present invention is similar to the embodiment shown in FIGS. 2 a-2 b, with the addition of STI regions 104 surrounding device pairs 101 and 102. By surrounding device pairs 100 and 102 with STI regions 104, sidewalls of source regions 106 and a source contact (not shown) exposed to epitaxial layer 128 (see FIG. 3 b) are isolated and presented with a lower capacitive load, therefore resulting in a lower source-substrate parasitic capacitance than would be achievable in conventional designs.

FIG. 3 b shows a cross-sectional view of this preferred embodiment of device pair 156 taken at cross-sectional line 3 b-3 b of FIG. 3 a. As is shown, STI region 104 is adjacent to source contact sinker 126. In alternative embodiments that do not utilize a source contact sinker 126, STI region 104 can be placed directly adjacent to source regions 106 and/or well regions 124.

Turning to FIG. 4 a, a layout view of yet another preferred embodiment of the present invention is shown. This embodiment is similar to the embodiment shown in FIGS. 3 a-3 b, with the addition of STI regions 104 c placed between drain contacts 114. The placement of STI regions 104 c reduces the surface area of the drain contact region 110 exposed to epitaxial layer 128 (FIG. 4 b) beneath the LDMOS device pairs 100 and 101, thereby reducing parasitic drain-substrate capacitance. In alternative embodiments that do not have epitaxial layer 128, STI regions 104 c reduce the capacitance of drain regions 108 to substrate 130 (see FIG. 4 b).

FIG. 4 b shows a cross-sectional view of this preferred embodiment of device pair 158 taken at cross-sectional line 4 b-4 b of FIG. 4 a. STI region 104 c is shown within drain region 108. STI region 104 is adjacent to source contact sinker 126. In alternative embodiments that do not utilize a source contact sinker 126, STI region 104 can be placed directly adjacent to source regions 106 and/or well regions 124. Alternatively, in other embodiments, STI regions 104 adjacent to source contact sinkers 126 can be omitted.

Returning to FIG. 1 c, fabrication of STI regions 104 according to preferred embodiments of the present invention is typically performed after epitaxial layer 128 is created. First, a chemical mechanical polishing (CMP) stop layer is deposited over the surface of epitaxial layer 128. In alternative embodiments without epitaxial layer 128, the CMP stop layer is deposited directly on the surface of substrate 130. According to a preferred embodiment, the CMP stop layer includes a 5 nm SiO₂ layer overlying substrate 130, on top of which a 200 nm Si₃N₄ layer is deposited. Next, a trench hard mask is deposited on top of the CMP stop layer. This hard mask is typically made from BPSG and deposited to a thickness of about 500 nm.

Resist is deposited over the hard mask and exposed lithographically according to a mask pattern. In a preferred embodiment of the present invention, the mask pattern defines the location of STI trenches 104 located according to the embodiments of the invention described hereinabove. Once the resist is exposed, the BPSG hard mask is etched and the resist is stripped using conventional techniques.

Using the BPSG hard mask, trenches in STI regions 104 are etched to a depth of between about 300 nm and about 700 nm. In other embodiments, the trench depth is preferably between about 200 nm and about 1000 nm. The opened silicon then undergoes a thermal oxidation step. Because STI regions 104 underlie regions of gate material, for example, under gate connections 102 the trenches 104 are filled with oxide using an HDP process. The HDP oxide deposition process is preferable compared to a conventional embodiment of LOCOS isolation for power devices to avoid the problem of SiN becoming embedded into the oxide, as is the case with thermally grown oxide used in conventional embodiments. The existence of such SiN particles underneath gate 103 is typically undesirable because it can lead to gate oxide failure by a mechanism known in the art as the Kooi effect. In alternative embodiments of the present invention, however, other processes besides HDP can be used which can create an oxide that promotes gate oxide reliability. For example, a low pressure chemical vapor deposition (LPCVD) of tetraethyl orthosilicate (TEOS) followed by a densification step can be used in place of HDP in other embodiments.

After the trenches in STI regions 104 are filled with oxide, a reactive ion etch (RIE) is used to remove oxide in non-STI regions in order to facilitate subsequent planarization. A CMP is then performed to remove most of the oxide (approximately 70%) from the surface of the stopping layer. Next, an oxide recess step, such as a deglaze, is performed to adjust the step height of STI regions 104 followed by a hot phosphoric acid etch of the Si₃N₄ pad nitride. A sacrificial oxide step is performed followed by the deposition of the gate oxide. The fabrication process then continues with the creation of the LDMOS devices, as hereinbefore described according to conventional techniques.

It will also be readily understood by those skilled in the art that materials and methods may be varied while remaining within the scope of the present invention. It is also appreciated that the present invention provides many applicable inventive concepts other than the specific contexts used to illustrate preferred embodiments. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. 

1. A semiconductor device comprising: a layer of insulating material disposed over a semiconductor body, and a gate electrode disposed over the layer of insulating material, the gate electrode comprising a first region of gate electrode material having a length, width, a first end at an end of the length and a second end at end of the length opposite the first end; a source region disposed within the semiconductor body, the source region adjacent the first region of gate electrode material along the width of the first gate region of gate electrode material; a drain region disposed within the semiconductor body, the drain region adjacent the first region of gate electrode material along the width of the first region of gate electrode material opposite the source region; a gate connection comprising a second region of gate electrode material that extends away from the width of the first region of the gate electrode material and is electrically coupled to a contact region, wherein the second region of gate electrode material couples to the first region of gate electrode material along the width of the first region of gate electrode material between the first and the second end; and a first insulating region disposed beneath the gate connection.
 2. The semiconductor device of claim 1, further comprising a second insulating region disposed within the semiconductor body adjacent to an end of the source region, the first region of gate electrode material, and the source region, wherein the second insulating region extends along a length of the source, and wherein the second insulating region extends underneath a portion of the first region of gate electrode material extending past the source region and the drain region.
 3. The semiconductor device of claim 1, further comprising: a plurality of drain contact regions, wherein each drain contact region comprises: a doped region disposed within the drain region, and a contact disposed over the drain region, wherein the doped region electrically couples the contact to the drain region; and a plurality of third insulating regions disposed on the semiconductor body between the plurality of drain contact regions.
 4. The semiconductor device of claim 1, further comprising a second insulating region adjacent to an edge of the semiconductor device, the second insulating region extending to an edge of an adjacent semiconductor device.
 5. The semiconductor device of claim 4, wherein the insulating region adjacent to the edge of the semiconductor device is adjacent to the edge of the device along a length of the source region.
 6. The semiconductor device of claim 1, wherein the source region is electrically coupled to a semiconductor substrate by a sinker.
 7. The semiconductor device of claim 1, further comprising a field plate disposed over a portion of the gate electrode.
 8. The semiconductor device of claim 1, further comprising an epitaxial layer disposed on the semiconductor body.
 9. The semiconductor device of claim 1, further comprising: a second insulating region disposed within the semiconductor body adjacent to an end of the source region, the first region of gate electrode material, and the source region, wherein the second insulating region extends along a length of the source, and wherein the second insulating region extends underneath a portion of the first region of gate electrode material extending past the source region and the drain region; a plurality of drain contact regions, wherein each drain contact region comprises: a doped region disposed within the drain region, and a contact disposed over the drain region, wherein the doped region electrically couples the contact to the drain region; and a plurality of third insulating regions disposed on the semiconductor body between the plurality of drain contact regions.
 10. The semiconductor device of claim 9, further comprising: a field plate disposed over a portion of the gate electrode; and an epitaxial layer disposed on the semiconductor body.
 11. The semiconductor device of claim 10, further comprising a fourth insulating region adjacent to an edge of the semiconductor device, the fourth insulating region extending to an edge of an adjacent semiconductor device.
 12. The semiconductor device of claim 11, wherein the fourth insulating region adjacent to an edge of the semiconductor device is adjacent to the edge of the device along a width of the source region.
 13. The semiconductor device of claim 1, wherein the semiconductor device is an LDMOS device,
 14. The semiconductor device of claim 1, wherein the first insulating region is an STI region.
 15. A semiconductor device, the semiconductor device comprising: a drain region disposed within a semiconductor body; a plurality of gate regions disposed over the semiconductor body, the plurality of gate regions disposed on opposite sides of the drain region along a width of the drain region, the gate region having a length, width, first end and second end opposite the first end, wherein the gate regions comprises gate electrode material; a plurality of source regions disposed within the semiconductor body, each of the plurality of source regions disposed adjacent to a gate region along a width of the gate region; and a plurality of gate contact regions disposed over the semiconductor body adjacent to each source region, each gate contact region comprising: a connection region of gate electrode material electrically coupled to one of the plurality of gate regions, at a location between the first end and the second end, a contact disposed over a portion of the connection region, and a first insulating region disposed on the semiconductor body beneath the connection region.
 16. The semiconductor device of claim 15, wherein at least two gate contact regions are disposed on opposite sides of the semiconductor device adjacent to widths of the source region.
 17. The semiconductor device of claim 16, wherein the first insulating regions in each of the at least two gate contact regions are connected to each other by a joining insulating region, the joining insulating region bisecting the drain region and channel regions between the at least two gate contact regions.
 18. The semiconductor device of claim 17, further comprising a second insulating region disposed on the semiconductor body adjacent to ends of the source regions, the gate regions and the drain region, wherein the second insulating region extends along lengths of the source regions and a lengths of the drain region, wherein the second insulating region extends beneath portions of the gate regions extending past the source region and the drain region.
 19. The semiconductor device of claim 18, further comprising: a plurality of drain contact regions, wherein each drain contact region comprises: a doped region disposed within the drain regions, and a contact disposed over the doped region, wherein the doped region electrically couples the contact to the drain region; a plurality of third insulating regions disposed on the semiconductor body between the plurality of drain contact regions; and a fourth insulating region adjacent to an edge of the semiconductor device, the fourth insulating region extending to an edge of an adjacent semiconductor device, wherein the insulating region adjacent an edge of the device is adjacent to the edge of the semiconductor device along a width of the source region.
 20. The semiconductor device of claim 15, further comprising a second insulating region adjacent an edge of the semiconductor device, the second insulating region extending to an edge of an adjacent semiconductor device.
 21. The semiconductor device of claim 20, wherein the second insulating region adjacent to an edge of the semiconductor device is adjacent to the edge of the semiconductor device along a width of the source region.
 22. The semiconductor device of claim 15, further comprising: a plurality of drain contact regions, wherein each drain contact region comprises: a doped region disposed within the drain regions, and a contact disposed over the doped region, wherein the doped region electrically couples the contact to the drain region.
 23. The semiconductor device of claim 15, wherein the plurality source regions, plurality of gate regions and the drain region comprise a pair of LDMOS devices.
 24. The semiconductor device of claim 23, further comprising a field plate disposed over a portion of each gate region.
 25. The semiconductor device of claim 23, further comprising a sinker, the sinker electrically coupling each source region to a semiconductor substrate.
 26. The semiconductor device of claim 15, wherein the first insulating region comprises an STI region.
 27. The semiconductor device of claim 26, wherein the STI region comprises HDP oxide
 28. The semiconductor device of claim 26, wherein the STI region comprises an insulating material to a depth of between 200 nm and 1000 nm.
 29. A semiconductor device comprising: a plurality of LDMOS device pairs disposed on a semiconductor body of a first conductivity type, at least one LDMOS device pair comprising: a shared drain region disposed on the semiconductor body, the shared drain region comprising a highly doped drain contact region disposed within a lightly doped drain region, the shared drain region being of a second conductivity type opposite the first conductivity type, a plurality of gate regions disposed adjacent to the shared drain region, each of the plurality of gate regions comprising a gate dielectric disposed on the semiconductor body and a gate electrode disposed over the gate dielectric, the gate electrode comprising polysilicon, wherein each gate region defines a channel region below each gate region, a plurality of field plate regions, each field plate region disposed over at least a portion of each gate region, wherein the field plate electrically shields the gate region from a portion of the shared drain region. a plurality of source regions disposed adjacent to each gate region opposite the shared drain region, the source region comprising a doped region of the second conductivity type, and a plurality of gate connection regions adjacent to the plurality gate regions, the plurality of gate connection regions comprising polysilicon disposed over a gate connection STI region, the gate connection STI region disposed in the semiconductor body, wherein each gate connection region is electrically coupled at least one of the gate regions, and wherein the gate connection region is coupled to a portion of the gate region between a first end of the gate region and a second end of the gate region opposite the first gate region; and a surrounding STI region surrounding at least one pair of LDMOS devices.
 30. The semiconductor device of claim 29, wherein the drain contact region of each shared drain region comprises a drain isolating STI region disposed within the drain contact region.
 31. The semiconductor device of claim 29, further comprising a sinker of the second conductivity type, the sinker electrically coupling one of the plurality of source regions to a semiconductor substrate.
 32. The semiconductor device of claim 31, wherein the gate connection STI regions comprise HDP oxide, and wherein the gate connection STI regions, the surrounding STI regions, and the drain isolating STI regions comprise insulating material of a thickness between about 200 nm and 1000 nm.
 33. The semiconductor device of claim 32, wherein the first conductivity type is p-type and the second conductivity type is n-type.
 38. A semiconductor device comprising: a layer of insulating material disposed over a semiconductor body, and a gate electrode disposed over the layer of insulating material, the gate electrode comprising a first region of gate electrode material having a length, width, a first end at an end of the length and a second end at end of the length opposite the first end; a source region disposed within the semiconductor body, the source region adjacent the first region of gate electrode material along the width of the first gate region of gate electrode material; a drain region disposed within the semiconductor body, the drain region adjacent the first region of gate electrode material along the width of the first region of gate electrode material opposite the source region; a gate connection comprising a second region of gate electrode material that extends away from the width of the first region of gate electrode material and is electrically coupled to a contact region, wherein the second region of gate electrode material couples to the first region of gate electrode material along the width of the first region of gate electrode material between the first and the second end; and a first insulating region disposed beneath the gate connection adjacent to portion of a width of the drain region. 